Time-share transmitter

ABSTRACT

A time-share transmitter for providing parallel-to-serial conversion of information includes a triggered pulse generator for developing the output information and time-share receiver synchronizing pulses in time separated form. A flip-flop triggered by a first one-shot multivibrator generates timing pulses for triggering the pulse generator as well as initiating operation of a multistage parallel-to-serial converter which converts the information to serial form. The serial output of the converter is connected to an AND logic circuit having a second input from the flip-flop, and the output of the AND circuit supplies the information pulses to the triggered pulse generator.

155-69? AJ 233 6X x3764 e Z United Sta J'Z/ AID Jones et a]. 1 Apr. 10,1973 1 TIIVlE-SHARE TRANSNIITI'ER [56] References Cited [75] Inventors:Clifford M. Jones, Waynesboro, UNITED STATES PATENTS :2" 3; Hmde'hschenec' 3,058,065 10/1962 Freeman et al. ..340/151 3,253,260 5/1966Hawley ..340/151 Ass g ee: General Company Schenec 3,463,887 llO "178/53tady Primary Examiner-John W. Caldwell [22] Filed: Dec. 17, 1970Assistant Examiner-Marshall M. Curtis Appl. No.: 99,192

Related US. Application Data Attorney-Paul A. Frank et a1.

[57] ABSTRACT A timeshare transmitter for providing parallel-to-seria!conversion of information includes a triggered pulse generator fordeveloping the output information and time-share receiver synchronizingpulses in time separated form. A flip-flop triggered by a first one- LS.Cl IIIIIIIII R, K Shdt multivibrator generates pulses for trigger-340/334 ing the pulse generator as well as initiating operation 51 Int.c1. .0091 9/36, 008C 15/06 multistage P2113115140-51311a1 which [58]Field of Search ..340/147 R, 147 S11. vans the infohhatim Serial fohh-The Serial Output 3 0 3 5 163, 5 178/17 R 50' 52 5 of the converter isconnected to an AND logic circuit 250 99 having a second input from theflip-flop, and the output of the AND circuit supplies the informationpulses to the triggered pulse generator.

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C/flY'orc/M Jones, John D. Hanna en, J,

SHEET 9 OF 9 PATENTEB ATP. 1 0 2. 5

- Mama...

TIME-SHARE TRANSMITTER This is a division of application Ser. No.778,218, filed Nov. 22, 1968, now U.S. Pat. No. 3,590,508, which in turnwas a division of application Ser. No. 449,l77, filed Apr. 19, 1965, nowU.S. Pat. No. 3,432,846.

Our invention relates to improvements in an illuminated display signwherein the display presented on the sign may be of the moving ornonmoving type, and in particular, to improvements in the display signdescribed in our copending patent application Ser. No. 422,227, filedDec. 30, l964, now U.S. Pat. No. 3,384,888, entitled Optical Apparatus"and assigned to the assignee of this application.

The above-identified patent application Ser. No. 422,227, describes allsolid-state device display signs which may be of the moving (traveling)message type, or the nonmoving but changing message type includingtime-temperature signs and scoreboards. Such copending patentapplication includes embodiments of the basic solid-state electroniccircuits forming the complete sign in addition to particular circuitfeatures such as provision for varying speed of travel of the charactersacross the display sign from a maximum speed to a complete stop in afinite or infinite number of increments, variation of speed of travelcontrol within sections of the display to obtain the optical effect ofstretching or compressing of the characters, and a variation of lampintensity from maximum brilliance to a dark condition.

The sign described in the copending application in cludes a bank ofelectric lamps mounted in a desired arrangement of rows and columns onone or more interconnected display panel sections or modules. The lampsare controllably illuminated in a desired sequence on a column-by-columnbasis to obtain a desired display on the sign. Each lamp is connected incircuit relationship with an associated solid-state device which, whenin its conductive state, supplies electrical power to the associatedlamp to causeillu mination thereof. The particular state (conductive ornonconductive) of each solid-state device is controlled by an electroniccircuit of the logic transfer-type connected in circuit relationshiptherewith, the logic transfer circuits associated with each particularrow of lamps on one display panel section being serially connected toform what is known in digital computer technology as a shift registercircuit. The logic utilized by the logic transfer circuits is generatedby an information circuit which converts input information intoelectrical pulse form corresponding to the desired sequence of lampillumination, the output of the information circuit being connected toan input of a first logic transfer circuit associated with each row oflamps on the first (extreme right end of the sign as viewed by anobserver) display panel section. A second electronic circuit, having anoutput common to all of the logic transfer circuits on a display panelsection, provides electrical signals for switching the logic from thelogic transfer circuits associated with one column of lamps to the logictransfer circuits associated with the next successive column of lamps.An electronic clock circuit, having an output connected to an input ofthe second electronic circuit, determines the speed of logic switchingbetween logic transfer circuits associated with adjacent columns oflamps.

The present patent application is directed to additional circuitfeatures for producing other desired optical effects on the displaysign. These additional features are not limited in their application tosolid-state display signs, but may also be employed in otherelectrically or even mechanically controlled display signals as well asother logic memory devices.

Therefore, one of the principal objects of our invention is to providenew and improved circuits for use in logic memory devices.

Another object of our invention is to provide an improved system forcontrolling multiple remote apparatus with a single information channel.

A still further object of our invention is to provide a light emittingdiode link as a data transmission system.

Another object of our invention is to provide an optional inputinfonnation circuit for direct entry of v messages to be presented on adisplay sign.

Another object of our invention is to provide a circuit for circulatinga particular message along a particular portion of the sign.

A further object of our invention is to provide a circuit for invertingthe characters on the display sign.

A further object of our invention is to provide a circuit for obtainingnegative writing on the sign wherein the characters comprisenonilluminated lamps on an illuminated lamp background.

Another object of our invention is to provide a circuitfor causingmotion of the characters on the display sign in a reverse direction.

A still further object of our invention is to provide a circuit forforming a message on the display sign by controlling illumination of thelamps on a row-by-row basis instead of the conventionalcolumn-by-column.

A further object of our invention is to provide a circuit for decreasingthe tailing effects produced by the slow extinguishment of lamps in atravelling message display.

Another object of our invention is to provide a circuit forautomatically stopping a travelling message at a particular point on thesign.

A further object of our invention is to provide a circuit for generatinga new message while the old message is displayed on a nonmoving messagesign.

A still further object of our invention is to provide a structure forseparating the illumination effects of adjacent lamps on the sign andfor providing cooling thereof.

Briefly stated, we provide a plurality of circuits for obtaining thehereinabove described objects of our invention. In particular, weprovide several switching circuits for providing a direct entry ofmessages on the sign, for circulating a particular message along aparticular portion of the sign, for inverting the characters on thesign, for obtaining negative writing on the sign, and for forming amessage on the sign by controlling illumination of the lamps on arow-by-row basis. The switching circuits may be of the electronic ormechanical type.

Various of the electronic circuits described in the above-identifiedcopending patent application may be modified in accordance with ourpresent invention for causing motion of the characters on the displaysign in a reverse direction, for decreasing the tailing effects producedby slow extinguishment of the lamps, for stopping (freezing) aparticular travelling message along a particular section of the sign,and for generating a new message while the old message is beingdisplayed on a nonmoving message sign.

The structure of a cover member for the lamps on the sign provides bothseparation of the illumination effects of adjacent lamps and coolingthereof.

Finally, an electronic circuit including a light emitting diode obtainsa wide bandwidth optical link which finds general application in datatransmission systems and is illustrated specifically for controlling asecond travelling message sign located remotely from a first sign.

The features of our invention which we desire to protect herein arepointed out with particularity in the appended claims. The inventionitself, however, both as to its organization and method of operation,together with further objects and advantages thereof, may best beunderstood by reference to the following description taken in connectionwith the accompanying drawings, wherein like parts in each of theseveral figures are identified by the same reference characters, thesame reference characters being employed for similar elements in FIGS.1, 8, 9 and 11 as in corresponding FIGS. 2 through 4, and 11 in theabove-identified copending patent application, and wherein:

FIG. 1 is a simplified block diagram of a display sign constructed inaccordance with U.S. Pat. No. 3,384,888;

FIG. 2 is a block diagram of a light emitting diode optical link systemfor transmitting data;

FIG. 3a is a block diagram of the transmitter section of the lightemitting diode optical link and FIG. 3b illustrates the timing sequenceof electrical signals at various points in the transmitter;

FIG. 4a is a block diagram of the receiver section of the light emittingdiode optical link and FIG. 4b illustrates the timing sequence ofelectrical signals at various points in the receiver;

FIG. 5 illustrates a switching circuit diagram for obtaining circulationof a message along a particular portion of the sign, inversion of thecharacters comprising the message, and a disappearance or tunneling of amessage at a first section along the sign and a reappearance of themessage at a section further along the sign;

FIG. 6a and 6b illustrate a switching circuit diagram for an optionalinput information circuit which provides direct entry of messages at anyselected portion of the sign as illustrated in FIG. 5;

FIG. 7 illustrates a switching circuit diagram for obtaining negativewriting on the sign wherein the characters comprise nonilluminated lampson an illuminated lamp background;

FIG. 8 is a schematic diagram ofa circuit for causing motion of thecharacters on the sign in a reverse direction and also for decreasingthe tailing effects produced by slow extinguishment of lamps in atravelling message display;

FIG. 9a is a schematic diagram of a circuit for automatically stoppingor freezing a particular travelling message along a particularsection ofthe sign and FIG. 9b illustrates such operation on a 2i module sign;

FIG. 10 is a switching circuit diagram for controlling illumination ofthe lamps on a row-by-row basis;

FIG. 11a is a circuit diagram for generating a new message while the oldmessage is displayed on a nonmoving message sign and FIG. 11billustrates the timing sequence of electrical signals at various pointsin the circuit; and

FIG. 12 is a perspective view of a structure for separating theillumination effects of adjacent lamps on the sign and for providingcooling thereof.

Referring now to FIG. 1 there is shown a simplified block diagram of anilluminated display sign which is described in detail in theabove-identified US. Pat. No. 3,384,888. Reference is made to U.S. Pat.No. 3,384,888 for the details of the specific components that comprisethe sign, but for convenience, the following summary of an illuminatedtravelling message sign is provided. For exemplary purposes only, thesign is illustrated in FIG. 1 as comprising two serially connecteddisplay panel sections 20, 21 upon which are mounted a bank ofpredetermined number of lamps in a desired arrangement of rows andcolumns. The lamps are controllably illuminated in a desired sequence ona column-by-column basis to obtain a desired optical display or messageon the sign. In the particular embodiment of the sign installed in theGeneral Electric Progressland Pavilion at the 1964-65 World's Fair, eachlamp is connected in circuit relationship with a solid-state controlledconducting device which, when in its conductive state, supplieselectrical power to the associated lamp to cause illumination thereof.The particular state (conductive or nonconductive) of each solid statedevice is controlled by an electronic circuit of the logic transfer typeconnected in circuit relationship therewith such that the conduction ofthe solidstate devices, and hence the illumination of associated lamps,is controlled in a desired sequence to thereby obtain the desireddisplay on the sign. The logic transfer circuits associated with eachparticular row of lamps on a display panel section are seriallyconnected to form a shift register circuit. Thus, in the case of a signhaving characters displayed thereon of height equal to seven rows oflamps, seven shift register circuits comprise the logic transfercircuits associated with each display panel section. Each of the shiftregister circuits has a number of stages equal to the number of lamps inthe associated row on that particular display panel section. Eachdisplay panel section is of sufficient width (in columns of lamps) topresent one or more characters thereon, in many cases a single displaypanel section comprising the entire length of the sign.

The component which determines the message presented on the sign is, ingeneral, contained within a control console located indoor and remotefrom the display panels. The remote control console includes aninformation circuit 24 which converts an information input intoprescribed electrical logic signals V of pulse form corresponding to adesired sequence of lamp illumination (the message displayed on thesign), an electronic clock circuit 25 which generates electrical pulses+V, at a substantially constant frequency wherein the frequencydetermines the speed of transmission of the logic through the logictransfer circuits and thus determines the speed of travel of charactersacross the sign, and may, if desired, further include a lamp intensitycontrol circuit 26 which provides control (voltage +V,,) of lampbrightness on the sign from maximum brilliance to a dark condition in aninfinite number of increments.

A second output of clock circuit 25 is connected to information circuit24 to provide synchronization of the generated logic with the switchingof the logic from one column of lamps to the next. An electronic circuitdesignated pulse generator and voltage switch 32 provides electricalsignals +V +V,, in response to the clock circuit pulses for switchingthe logic from column to column on the display sign, that is, from thelogic transfer circuits associated with one column of lamps to the logictransfer circuits associated with the next successive column of lamps inaccordance with the logic generated in information circuit 24. A powersupply circuit 33 is supplied with alternating current electrical powerthrough conductors 34 and provides electrical power to the variouselectronic components located on the display panel, the logic transfercircuits and circuits 32 and 33, in general, being located on suchpanel. The number of interconnecting electrical conductors between theremote control console and the display sign proper is, in general, equalto the number of rows of lamps on a display panel section (conductors27), a conductor 28 for controlling speed of travel across the displaysign, a common signal return conductor 40 and a conductor 29 tointerconnect the sign with lamp intensity control circuit 26, ifemployed.

The two display panel sections 20, 21 illustrated in FIG. 1 may comprisesections of one sign, or each may comprise a complete sign, remote fromthe other, whereby the same message is presented at two remotelocations. The number of electrical conductors interconnecting the signproper with the remote control console also equals the number ofconductors interconnecting two display signs located remotely from eachother and adapted to display the same message thereon. However, it isoften desirable to completely eliminate all of the electrical conductorswhich interconnect two remotely located signs displaying the samemessage. One arrangement for obtaining the necessary coupling betweentwo remotely located signs without electrical conductors is a lightemitting diode optical link system shown in block diagram form in FIG.2, the details of the transmitter and receiver portions thereofillustrated in FIGS. 3a and 4a, respectively. The light emitting diodelink is a multiplex data transmission system which permits transmissionof information over considerable distances and will now be describedwith specific application to a connection between two remote displaypanels 38, 45 of a travelling message sign. Referring particularly toFIG. 2, there is shown a multiplex circuit used to time-share the lightemitting diode optical link for 7 channel operation. The 7 channels areused to provide the logic connection between the 7 rows of logictransfer circuits on each of the two remotely located display panels 38,45.

The time-shared light emitting diode optical link system of FIG. 2comprises an information circuit which may include a tape reader,decoder-encoder, and readout display wherein the decoder-encoder decodesseven bit encoded characters on tape (in the particular case wherein theinformation input is encoded on tape and there are seven rows ofinformation) to one of 53 unique outputs and converts the single uniquedecoder output to a selected combination of 42 outputs (in the casewherein 7 rows by six columns of lamps determine one character) used bythe readout display. The readout display is a buffer circuit fortemporarily storing the information prior to its transfer and display onthe sign. Alternatively, and in many cases, preferably, the informationcircuit comprises a direct entry circuit for generating the desiredinformation logic without employing the intermediate decoder element.Examples of such direct entry circuits are illus trated in FIG. 6b, themanual keyboard entry device being employed in FIG. 2. The output ofdirect entry circuit 100 is connected to an encoder 36 of conventionaldesign (such as a diode matrix, resistor matrix, or magnetic core)having the parallel 42 outputs described above connected to a 42 bitcharacter display on display panel 38. The resulting display on panel 38is then shifted or stepped along the panel by a clock circuit 25, onecolumn at a time, thus functioning as a travelling message sign.Transfer of the displayed information from display panel 38 to displaypanel 45 requires transfer of seven bits of information (one per row)for each column-by-column logic switching step. A single channel lightemitting diode optical transmitter 42 is the communication connectionbetween the two remote display panels. The optical transmitter is timeshared for each of the seven bits of logic information transmitted ineach column-by-column logic switching step. The time sharing function isprovided by time-share transmitter 39 which is shown in greater detailin FIG. 3a.

A block diagram of the time-share transmitter 39 illustrated in FIG. 2is shown in FIG. 3a. The time-share transmitter converts the seven-butoutput V of display panel 38 to a form which can be transmitted over asingle channel light emitting diode optical link. The maximum rate ofinformation transfer is, in general, deter mined by the ability of theincandescent lamps on the sign to switch, that is, turn on and off,without produc ing the optical effect of excessive smearing as themessage travels across the sign. This maximum rate of informationtransfer without excessive smearing is approximately 20 logic switches(cycles) per second. However, for some effects such as in a changing(nontravelling) message sign, and for fast clearing of the sign, thatis, fast removal of the message, it is desirable to transfer informationat the fastest rate available which is determined by the solid statedevice commutation limits determined by the power line frequency. Thisfastest commutation rate determined by power line frequency is normallyI20 commutations per second (on a 60 cps power line). At this I20 cycleper second rate, the multiplex clock rate of clock circuit 25 fortransferring logic from a seven column display is a minimum of 1,680clock pulses per second (one synchronizing pulse and one information bitpulse per output). For convenience, a 2 kilocycle rate is selected forthis particular application.

The time-share transmitter circuit 39 and data transmitter timingsequence associated therewith will now be explained with particularreference to FIGS. 3a and 3b, respectively. Assume for referencepurposes that at time equal zero, common buss switched voltage +V isswitched to 0 volts. The switching of voltage +V is accomplished in thepulse generator and voltage switch circuit 32 on display panel 38 asdescribed in the copending patent application. When this pulse +V isreceived from display panel 38, a one shot multivibrator circuit 46generates a pulse of 7.25 milliseconds (MS) duration as seen in FIG.3(b)2. The 7.25 millisecond pulse initiates a l kilocycle per secondtriggered square wave generator circuit 47 which functions as a timinggenerator to generate pulses at a l kilocycle per second rate asillustrated in FIG. 3(b)3. The output of triggered square wave generatorcircuit 47 is applied to pulser circuit 48, a triggered pulse generator,for providing receiver synchronization, to a logic AND circuit 49, andto a one shot multivibrator 50 which provides a 0.25 millisecond timedelay. The rising edge of the 0.25 millisecond pulse advances a sevenstage parallel-to-serial converter circuit 51 one stage at a time toprepare it for readout of the next information bit stored therein andthereby convert the parallel seven-output V,,, of the logic transfercircuits of display panel 38 to a serial form. The rising edge of theone Itilocycle (lKC) square wave pulse triggers pulser circuit 48 forsynchronizing the receiver to the transmitter, and the falling edgeinitiates the AND circuit 49 and multivibrator 50.

The timing sequence of the 0.25 millisecond delay pulse is illustratedin FIG. 3(b)4 as being initiated at the fall time of the l kilocyclesquare wave pulse. The second input to parallel-to-serial convertercircuit 51, the parallel seven bit input V is applied during the timeinterval of the pulse +V Thus, the: output of time-share transmitter 39consists of seven synchronizing pulses equally spaced, and up to seveninformation (logic) bit pulses, each pulse separated by 0.5 millisecondsas illustrated in FIG. 3(b)5 wherein the logic bit pulses are designatedby dash line form. The output of pulser circuit 48 is thus seen to beoperable at the two kilocycle per second rate hereinabove selected, andis connected to the anode of a light emitting diode in the opticaltransmitter circuit 42 which also includes a suitable lens for focusingthe output of the diode.

The receiver portion of the time-shared light emitting diode opticallink is illustrated generally in FIG. 2 as comprising an opticalreceiver circuit 43, a time-share receiver 44 and a display panel 45which are all located remote from the transmitter portion of the system.Optical receiver circuit 43 includes a photodetector which may be of thephotoelectric cell type and a suitable lens for focusing the lightemitted by the optical transmitter 42 upon the photodetector.

Details of the time-share receiver and data receiver timing sequenceassociated therewith are shown in FIGS. 4a and 4b, respectively. Theoutput of optical receiver 43 is amplified and shaped by a 0.2millisecond one shot multivibrator circuit 81 which also includes apreamplifier stage. The input to the 0.2 millisecond one shotmultivibrator 81 is illustrated in FIG. 4(b)l and the stretched outputsignal of the multivibrator circuit 81 is shown in FIG. 4(b)2 whereinthe synchronizing pulses are designated by solid line and theinformation bit pulses by dash lines corresponding to the pulser 48output in FIG. 3(b)5. The stretched output signal of the 0.2 millisecondone shot multivibrator initiates a l millisecond one shot multivibrator82 which generates the clock pulse +V,. to advance the logic on theremote display panel 45 by one column at the next 60 cycle zerocrossing. The synchronizing pulses (solid line pulses in FIGS. 4(b)1 and4(b)2 are time separated from the information (logic) bits by a 0.8millisecond one shot multivibrator circuit 83 and a bistable flip-flopcircuit 84 in the following manner. Flip-flop circuit 84 is set by therising edge of the 0.2 millisecond synchronizing pulse generated by oneshot multivibrator 81, and is reset" by the rising edge of the 0.8millisecond pulse generated by multivibrator 83. The setting andresetting of flip-flop circuit 84 at the 0.2 and 0.8 millisecond times,respectively, is provided as a first input to a logic AND circuit 85. Asecond input to the AND. circuit includes the output of the 0.2millisecond one shot multivibrator 81 which includes both synchronizingand information bit pulses. Reference to FIGS. 4(b)2 and 4(b)5 indicatesthat the only output that may be obtained from AND circuit 85 is theinformation bit pulse which, if it is present, exists between the 0.2and 0.8 millisecond edges of the flipflop 84 output. Thus, the output ofAND circuit 85 represents only logic information bits in serial formwhich upon serial-to-parallel conversion, command the associated logictransfer circuits of the remote display panel 45 and thereby controlillumination of corresponding lamps. A second output of flip-flopcircuit 84 represents the synchronizing pulses which serially advancethe logic in a seven stage serial-to-parallel converter 86 one stage ata time. Serial-to-parallel converter 86 is read out when the logic foreach column of lamps has been stored within the converter. the voltagepulse +V, initiating such readout of the converter and subsequenttransfer to the parallel seven-input V at the logic transfer circuits ofremote display panel 45. It should be noted that the first synchronizingpulse occurs 0.5 milliseconds after the reference time equal zero ofFIG. 3b, and each 60 cycle zero crossing occurs at approximately 8.3milliseconds. Thus, the zero crossing, which determines thecolumn-by-column logic transfer times, occurs at a time after thegeneration of all seven synchronizing and information bit pulses butwell within the IQ millisecond duration of the +V pulse of FIG. 4(b)3.

A good optical alignment between optical transmitter 42 and opticalreceiver 43 is obviously necessary for obtaining operation of thehereinabove described data transmitting system. In a particularapplication, at a distance of 200 feet between the optical transmitterand receiver, the signal level of the photodetector in optical receiver43 exceeded one volt whereas the optical receiver input sensitivity wasless than l0 millivolts.

Thus, the system can be operated at distances much greater than 200feet. The long life, semiconductor impedance compatability, and widebandwidth are some of the significant advantages of the light emittingdiode optical transmitter. In the particular application of the sevenchannel travelling message sign hereinabove described, the widebandwidth capabilities of the light emitting diode was such that thediode was in an on" or active state less than 2 percent of the time,thus the system has a capability for greatly increased informationhandling. Each of the components of the data transmission systemhereinabove described is of conventional design and thus the details ofthe block diagram are not illustrated. The aforementioned system mayalso be used with other more conventional single channel links such asradio frequency or wire pair rather than the light emitting diodeoptical channel described.

Referring now to FIG. 5, there is shown a circuit diagram for obtainingthe optical effects of circulation of a message, inversion of characterscomprising a message, and a disappearance or tunneling of a message at afirst point along the sign and the reappearance of the message at apoint further along the sign. In particular, there are shown two of thedisplay panel sections 21, 20 as illustrated in FIG. 1 and the sevenelectrical conductors interconnecting these two display panel sections.The circuit component for obtaining the optical effect of circulating aparticular message along a particular portion of the sign is a switchingcircuit 88 which as a nonactuated normal" (N) position, and an actuatedcirculate" (C) position. In the normal N position, the logic output V ofdisplay panel section 21 is undisturbed and the message continues onthrough the remainder of the sign. In the circulate C position of theswitch, the seven channel logic connection between adjacent displaypanel sections 21 and 20 is disconnected and the logic input V ofdisplay panel section 20 is connected to the output of display panelsection 20 which represents the end point of the circulation loop. It isto be understood that display panel section 21 in FIG. 5 is notnecessarily the first panel in the sign as shown in FIG. 1. Further,display panel section in FIG. 5 represents any desired number of displaypanel sections which comprise the message circulation loop, thecirculation loop display panel sections being located further along thesign from panel section 21. Any number of switching circuits 88 may beprovided along the length of the sign to obtain recirculation of one ormore messages, simultaneously, if desired. Switching circuit 88 as wellas the other switching circuits shown in FIGS. 5, 7, 8, 9, I0, 11 mayinclude switches of the electronic or mechanical type, switches of themechanical contact, relay-actuated type being illustrated forconvenience only. The seven movable arms of switch 88 are actuatedsimultaneously in response to a signal generated in a circulate command"control circuit 89 which is supplied with an appropriate signal tocommand operation of switch 88. Control circuit 89 is of conventionaldesign and may conveniently be located at the remote control console.

The actuation of the circulation switching circuit 88 causes arecirculation of any message or characters contained within thecirculation loop at the time of the switching. In many applications, itis desirable to circulate a particular message not included within thecirculation loop at that instant of time, and to obtaimthis particularfeature a second switching circuit 92 is employed to provide an optionalinput to the circulation loop. As illustrated in FIG. 5, switchingcircuit 92 has a nonactuated normal" (N) position and an actuatedoptional input" (0) position. In the normal N position, the logic outputV,, of display panelsection 21 is undisturbed and the normal messagecontinues on through the remainder of the sign. In the optional input 0position of the switch, the seven channel logic connection betweendisplay panel sections 21 and 20 is disconnected and the logic input Vof display panel section 20 is connected to an optional logic input, thelogic input V source. The seven movable arms of switch 92 are actuatedsimultaneously in response to a signal generated in an optional inputcommand" control circuit 93 which is of conventional design and may alsoconveniently be located at the remote control console. The optionalinput control is generally employed in conjunction with the circulatecontrol 89 to permit introduction of a desired message within thecirculation loop on the sign. The optional input control may beinitiated at a time when no characters or portion of a message arelocated within the circulation loop, or, alternatively, the first partof the optional input message may comprise suitable blanking informationbits to cause erasure of the previous characters contained within thecirculation loop. The sequence of operation of the circulate controlwhen employed with the optional input control is to first actuate theoptional input, and upon having the desired message within thecirculation loop, the circulate control is thence actuated and theoptional input simultaneously inactivated to complete the circulateloop.

In the circulate mode of operation, it may be desirable to tunnel themessage not being circulated around the portion of the sign containingthe circulating message, and to have the noncirculating message reappearat that point along the sign just subsequent to the circulation loop,that is, to have the noncirculating message disappear and reappear at asubsequent position along the sign. To accomplish this purpose, a thirdswitching circuit 94 is located at the portion of the sign wherein themessage is to reappear. This tunnel control switching circuit alsocomprises a plurality of two position switches, each switch having annonactuated normal" (N) position and an actuated tunnel" (T) position.In the normal N position, the logic output V or display panel section 20is undisturbed and the normal message passing through display panelsections 21, 20 continues on through the remainder of the sign. In thetunnel T position of the switch, the logic input V to display panelsection 19 is disconnected from the logic output V of display panelsection 20 and connected to the logic output V,, of display panelsection 21 which represents a point on the sign somewhere prior to theimmediately preceding display section. The seven movable arms of switch94 are actuated simultaneously in response to a signal generated in atunnel command control circuit 95 which is of conventional design andmay also conveniently be located at the remote control console. Thetunnel control may be initiated simultaneously with the circulatecontrol and optional input control, if desired, to produce thesimultaneous circulation of an optional message within the circulationloop and to have the normal sign message tunnel under such circulationloop and reappear on the sign at a point subsequent to the circulationloop.

A fourth switching circuit also located in the interconnectingconductors between display panel sections 21 and 20 obtains the opticaleffect of inversion of the characters comprising the message on thedisplay sign. Switching circuit 90 is also a two position switch, havinga nonactuated normal" (N) position and an actuated "inversion" (I)position. In the normal N position, characters that comprise the messageare not modified and the message continues on through the signundisturbed. In the inversion I position of the switch, the conductorsfrom the output of display panel section 21 are disconnected andreconnected to the input to display panel section in an inverserelationship. The six movable arms of switch 90 are actuatedsimultaneously in response to signal generated in an inversion commandcontrol circuit 91 which is of conventional design and may also belocated at the remote control console. A second inversion switchingcircuit may be located further along the sign to reinvert the charactersinto'their original condition, if desired.

FIG. 6a illustrates an input information circuit which may be used as adirect entry into the sign without employing a decoder as in the case ofthe information circuit 24 of FIG. 1 and described in the copendingpatent application. The direct entry input information circuit of FIG.6a comprises a stepping switch 96, as a particular method, which isconnected at one terminal end to a source of voltage +V. The movable armof switch 96 automatically moves sequentially across the contacts togenerate the logic that comprises the message to be displayed. Thelogic-making contacts indicate the message to be composed and areconnected to the associated encoder character within encoder 97 togenerate the particular logic corresponding to the letters of "GOODMORNING" in this particular illustration. Encoder 97 may comprise theencoding diode matrix 36 illustrated in FIG. 2 or other known encoderssuch as a resistor matrix or magnetic core, and has as an input a numberof electrical conductors equal to the different characters in themessage to be displayed. The output of encoder 97 comprises a number ofelectrical conductors equal to the number of logic transfer circuitsthat are employed in generating each character. Thus, in the particularapplication wherein one letter is comprised of lamps arranged in sevenrows and six columns, 42 conductors comprise the output of encoder 97,and these are connected to the respective logic transfer circuitscontained within a readout display that functions as a buffer circuit98. Buffer circuit 98 is employed for temporary storage of one characterprior to its transfer to the sign as is more fully described in thecopending patent application. The output of buffer circuit 98 is thelogic input V which may be provided as an input to the first displaypanel section of the sign or as the optional input in FIG. 5.

The advantage of the direct entry information input circuit illustratedin FIG. 6a is that it avoids the need for a decoder as employed in thecopending patent application and thus a more simplified informationcircuit 24 is obtained. FIG 6b illustrates the extension of the directentry concept in a circuit which provides for the selection of any oneof three direct entry information input circuits. A first of the threedirect entry circuits designated message maker 99 is the stepping switch96 illustrated in FIG. 6a. The output of message maker 99 comprises thenumber of electrical conductors required for connection to an encoder,the number of conductors being equal to the different charactersincluded within the message which is automatically generated by steppingswitch 96.

The second direct entry information input circuit is a manual keyboard100 wherein the particular characters comprising the message are punchedout on a typewriter device rather than being automatically preset as inthe stepping switch 96. The typewriter keys of keyboard 100 areconnected to a switching circuit having an output similar to the outputof the stepping switch of message maker 99. A third and automatic directentry information input circuit is the time-temperature circuit 101. Inthis third direct entry circuit, the information provided to the encoder97 is correct time and temperature which is typically provided on signsinstalled on banks and other buildings. The correct time information isprovided by a continuously running clock with an output in suitable formcompatable with the system shown in FIG. 6b, and the temperatureinformation is provided by a thermometer and suitable thermaltransducer. The output of the third circuit 101 thus comprises tenconductors associated with the 10 number characters, and may alsoinclude two additional conductors for designating temperatures above andbelow zero degrees Fahrenheit.

The GOOD MORNING message generated by the stepping switch 96 in FIG. 6ais also illustrated as being generated by message maker 99 in FIG. 6b.The manual keyboard 100 is also illustrated as adapted to form the GOODMORNING message as well as to provide an output consisting of numberswhich are the same as the logic output generated by the time-temperaturecircuit 101. Switch 102 thus pennits the choice of an automatic directentry information input as provided by message maker 99 or thetime-temperature circuit 101, or provides a manual direct entryinformation input provided by keyboard 100. The outputs of the threedirect entry information input circuits 99, I00, 101 are connected tothe input an encoder such as illustrated in FIG. 6a, the output of theencoder being connected to a buffer circuit which at its output providesthe logic signals V which may be provided at the first input to the signor as the optional input in FIG. 5.

The conventional method of writing on a sign, that is, forming thecharacters of a message on the sign, is to employ illuminated lamps forthe character on an nonilluminated lamp background. it may be desired,in some instances, to obtain the optical effect of negative writing onthe sign wherein the characters displayed comprise nonilluminated lampson an illuminated lamp background. The negative writing optical effectis obtained by inserting a switching circuit 104 in the electricalconductors interconnecting the logic transfer circuits of two adjacentdisplay panel sections, 21, 20 as illustrated in FIG. 7. Switchingcircuit 104 includes a two position switch and a simple transistorcircuit in each of the seven logic channels for inverting the logicbeing transmitted for display panel section 21 to display panel section20. The two position switch has a nonactuated positive writing (P)position and an actuated negative writing" (N) position. In thenonactuated P position, the logic output V of display panel section 21is undisturbed and thus the positive writing comprising illuminatedlamps on a nonilluminated lamp background is maintained. In the actuatedN position of the switch, the logic is inverted and a negative writingoptical effect is obtained. The seven movable arms of the switch areactuated simultaneously in response to a signal generated in a "negativewriting command control circuit 105 which may conveniently be located atthe remote control console. It is apparent from FIG. 7 that, when thelogic in each of the seven channels is inverted and the characterspresented on the sign are seven rows high, there is no border effect onthe sign to set off the negative written characters. In someapplications, it may be desirable to maintain a border of one row ofilluminated lamps at the top and bottom of the sign to more distinctlyset off the characters in their negative written state. To accomplishthis latter optical effect, either the characters presented on the signmust be programmed at the information input from seven to five rows orchannels in height, and the information input must also be programmed tocall for the appropriate logic to obtain illuminated lamps in the outertwo rows, or a nine row (two border rows) format might be used.

The conventional motion of the characters on the sign in a travellingmessage mode of operation is from the right end of the sign toward theleft end, as viewed by an observer, and this is defined as motion in theforward direction. It may be desired, in some instances, to reverse thedirection of motion of the characters, that is, to cause the charactersto move in a direction from the left end of the sign toward the rightend. The circuit of FIG. 8 obtains this motion in a reverse direction.FIG. 8 of the present application is FIG. 5 of the U.S. Pat. No.3,384,888 modified to obtain reverse motion on the sign of thecharacters comprising a travelling message. For purposes of review, thecircuit illustrated in FIG. 5 of the U.S. Pat. No. 3,384,888 will now bebriefly described with reference to the optical effect of charactermovement in the forward direction on the sign, that is, the transfer oflogic in this forward direction. FIG. 8 illustrates a schematic diagramof the component designated as pulse generator and voltage switchcircuit 32 and three stages of one row of the logic transfer circuits37, separated from component 32 by means of dashed line 53. Pulsegenerator and voltage switch 32 is comprised of transistor 54 connectedin an AND logic circuit, and transistor 55 connected in a circuit forobtaining a voltage +V switching function. A third circuit includingtransistor 56 provides a pulse +V,,,. generating function. The inputvoltages to pulse generator and voltage switch 32 include two full waverectified, filtered voltages -V,,, +V,,, and a full wave rectified,unfiltered voltage +V, supplied from the power supply circuit 33 in FIG.I, and the clock pulser +V generated by clock circuit 25. The clockcircuit output voltage +V,. is a DC voltage which periodically switchesto zero for the time interval of one of the clock pulses. A switchedvoltage common buss 57 is connected to the collector electrode oftransistor 55, and the presence or absence of switched voltage --V, onbuss 57 is determined by the mode of operation of transistor 55 whereinsuch transistor switches voltage +V, to buss 57 when in its conductivestate. During the time interval in which clock pulse +V,. is applied toterminal 61, transistors 54 and 55 are in fully conductive states andswitched voltage +V, is present on switched voltage common buss 57.Switched voltage +V, remains on buss 57 until such time that voltages+V,, and +V,. are concurrently at, or near, zero at which time thevoltage +V, on buss 57 switches to zero and remains at zero during thetime when voltage +V,, is near zero crossing. At such zero crossing, thepower system zero crossing time, transistors 54 and 55 are in anonconductive state. The three stages of logic transfer circuits 37include lamps 64, 65 and 66 (successive lamps in one row) each connectedto circuit relationship with a corresponding solid state controlledconducting device 67, 68 and 69, respectively. The solid state devices67, 68, 69 (illustrated as gate turnon silicon controlled rectifiers)are employed to carry both the logic and lamp power for the associatedlamps. Thus, during the conduction interval of solid state device 68, aDC current flows from lamp common buss 70 being supplied at terminal 63with voltage +V through lamp 65, blocking diode 71, and solid statedevice 68 to a common ground or signal return conductor 40 connected toterminal 62 maintained at zero volts. Lamp voltage +V is full waverectified, unfiltered, phase controlled voltage supplied from the powersupply circuit 33.

The operation of the logic transfer circuits 37 for the case wherein thelogic commands that the nonilluminated state of a particular lamp betransferred in a forward direction to the next subsequent lamp in thissame row of lamps is as follows: Assume that solid state device 68 isnonconductive whereby associated lamp 65 is nonilluminated and suchlogic is to be transferred to the logic transfer circuit which includeslamp 66 and solid state device 69. At steady state conditions, the anodeof solid state device 68 is at the switched voltage +V no clock pulse issupplied to terminal 61, and capacitor 74 becomes charged throughresistors 73, 75 and 77 to the voltage V, which is approximately 20volts as one example. Now, assume that a clock pulse +V is supplied toterminal 61 for approximately 8 milliseconds, a time interval ofsufficient duration to insure that only one zero crossing of voltage +Voccurs during the clock pulse interval. The concurrent presence of theclock pulse and zero crossing of voltage +V renders transistors 54 and55 nonconductive thereby switching voltage +V on switched voltage commonbuss 57 to zero, and during this short interval of time which may be inthe order of microseconds (the total time for transferring logic), allof the solid state devices 67,68, 69 in the logic transfer circuits arefully commutated off. The subsequent rise of voltage +V in a positivedirection after falling to zero causes transistors 54 and 55 to becomeconductive thereby reapplying voltage +V to the switched voltage com monbus 57. At this time, all of the solid state devices 67, 68, 69 are in anonconducting state and transistor 56 is momentarily rendered conductivethrough capacitor 78. The momentary conduction of transistor 56generates a voltage pulse +V,,,. on pulse common buss 79, capacitor 74maintains its charge during the short duration of pulse +V,,, and diode76 remains reverse biased since the voltage magnitude of pulse V is lessthan V and thus no gate current is supplied to solid state device 69 andit therefore remains nonconductive. Thus, the logic has been transferredfrom the circuit including lamp 65 and solid state device 68 to thecircuit including lamp 66 and solid state device 69 during the timeinterval of pulse +V,,,..

The operation of the logic transfer circuit in the case wherein theilluminated state of a lamp is transferred to the next subsequent lampin the same row in a forward direction is as follows: Assume that solidstate device 68 is conducting and associated lamp 65 is thereforesupplied with electrical power and is in an illuminated condition. Atthis time, the anode of device 68 is at a voltage of approximately 1volt, the voltage drop across device 68. Under these conditions,capacitor 74 is charged to the voltage at the anode of device 68, thatis, to approximately I volt. The sequence of operation of the pulsegenerator and voltage switch circuit 32 and the logic transfer circuits37 is the same as in the nonilluminated logic transfer case hereinabovedescribed through the step wherein transistor 56 momentarily becomesconducting and generates voltage pulse +V,,, on pulse common buss 79. Atthis time, diode 76 becomes conductive since the voltage magnitude ofpulse V,,, is approximately 10 volts as compared to the one voltagecharge on capacitor 74. The conduction of diode 76 causes a current flowthrough capacitor 74 to the gate of solid state device 69 therebycausing such device to become conductive. Thus, it can be seen that thelogic has been transferred from the circuit including lamp 65 and device68 to the circuit including lamp 66 and device 69. It thus follows thatcapacitor 74 is charged in its steady state condition (the intervalbetween logic transfer) to a voltage of approximately l volt if theprevious stage is on" (lamp illuminated),

and is charged to switched voltage V of approximately 20 volts if theprevious stage is off (lamp not illuminated).

In order to obtain reverse motion of the travelling message on the sign,the addition of a capacitor-resistor-diode circuit (74R, 75R, 76R) ineach of the stages of logic transfer circuitry is employed asillustrated in FIG. 8. The additional circuitry corresponds to theelements capacitor 74, resistor 75 and diode 76 employed in the forwardmotion of logic transfer (character travel). Thus, resistor 75R isconnected from the anode of solid state device 69 to the juncture ofcapacitor 74R and the cathode of diode 76R. The other end of capacitor74R is connected to the gate electrode of solid state device 68, and theanode of diode 76R is connected to pulse common buss 107. The threereverse motion elements resistor 75R, capacitor 74R and diode 76Rinterconnect one stage of logic transfer circuitry to the immediatelypreceding stage whereas the forward motion elements interconnect onestage to the immediately succeeding stage. The three reverse motionelements provide the same circuit function as corresponding forwardmotion elements resistor 75, capacitor 74, diode 76 and the circuitoperation for reverse motion of the characters on the sign will thus notbe described. A switching circuit 108 connected in the collectorelectrode circuit of transistor 56 determines the direction of motion ofthe travelling message on the sign. Switching circuit 108 is actuated inresponse to a signal generated in a motion direction command" controlcircuit 109 which is of conventional design and may conveniently belocated at the remote control console. Switching circuit 108 has anonactuated forward motion" (F) position and an actuated reverse motion"(R) position. In the forward F position, the momentary conduction oftransistor 56 generates voltage pulse +V on pulse common buss 79. In thereverse (R) position of the switch, the momentary conduction oftransistor 56 generates a voltage pulse +V,,., on pulse common bus 107.Operation of switching circuit I08 thus permits control of motion of atravelling message on the display sign in both directions of travel.

The lamps 64, 65, 66 used on the display sign in FIG. 8 are preferablyof a type having the shortest possible extinguishment time in order tominimize the tailing ef fects produced in travelling message displays.As an e"-- ample, the lamps employed in the General Electric World'sFair Progressland Pavilion are 6 watt, 13.5 volt gas-filled incandescentlamps. As described in U.S. Pat. No. 3,384,888, the speed of travel ofthe message across the sign may be varied and, at the higher speeds oftravel, tailing effects may be observed due to the noninstantaneousextinguishment of the lamps. This tailing effect, being undesirablesince it causes a smearing of the characters, may be decreased byemploying a time delay circuit 110 in the collector electrode circuit oftransistor 56 in the pulse generator and voltage switch circuit 32. Timedelay circuit 110 is inserted into the circuit by operation of switch 111 which may be activated from a command control circuit (not shown)located at the remote control console. Time delay circuit 110 is ofconventional design and provides a time delay in the order of 10 to 20milliseconds between the time at which transistor 56 is momentarilyrendered conductive by the reapplication of voltage +V to switch voltagecommon buss 57 and the subsequent time of generation of voltage pulse+V, The delay in the generation of voltage pulse +V,, thus delays theapplication of this logic transferring signal to the logic transfercircuits 37 until some time after all of the solid state devices 67, 68,69 have been commutated off. This delay in logic transfer therebyprovides a time delay between the time at which lamps in one column arein the process of being extinguished (the period in which the solidstate devices 67, 68, 69 are commutated off) and the time at which lampsin the next adjacent column are illuminated (upon transfer of logic tosuch next successive logic transfer circuits). A second arrangement (notshown) for decreasing tailing effects produced by the slowextinguishment of lamps in a travelling message display employs a gatedtime delay circuit in the emitter circuit of the unijunction transistorof FIG. 8 in U.S. Pat. No. 3,384,888 wherein such FIG. 8 circuit is thecomponent designated lamp intensity control circuit 26 in FIG. 1. Insuch second embodiment, clock circuit output +V is employed for gatingon the time delay and thereby inhibiting operation of the lampintensity-control circuit 26 for the prescribed time delay until thelamps in the previous column have been substantially extinguished.

FIG. 9a illustrates a circuit for obtaining the optical effect ofstopping or freezing" a selected travelling message along a particularportion (modules 8-19) of the sign while the remainder of the sign andany message thereon continues operating (moving) in a normal manner. Thecircuit for the freeze" control is an auxiliary circuit, similar inconstruction to the pulse generator and voltage switch circuit 32 andlogic transfer circuits 37 of FIG. 8 and used in conjunction therewith.The freeze" control circuit inhibits the clock pulses +V applied topulse generator and voltage switch circuit 32 to thereby inhibit logictransfer, one module at a time. Each module is defined as a displaypanel section of width sufficient to display one seven row by six columncharacter thereon, this type of modular construction being employedlinthe 1964-65 New York World's Fair General Electric Progressland Pavilionsign. In FIG. 9a, the freeze" control circuit is illustrated assupplying the clock pulses +V to the +V terminal 61 of pulse generatorand voltage switch circuits 32 associated with module numbers 8 through19, these particular modules being chosen as the freeze" control portionof the sign. For purposes of explanation, the portion of the freeze"control circuit corresponding to the pulse generator and voltage switchcircuit 32 is designated circuit 32a herein, and the portioncorresponding to the logic transfer circuits 37 is designated circuit37a. Circuit 32a of the freeze control circuit in FIG. 911 includes thepulse generator and voltage switch circuitry of FIG. 8 and a frequencydividing circuit 113 in the base electrode circuit of transistor 54 fordividing the frequency of the incoming clock pulses +V by six, six beingthe number of columns of lamps (and logic transfer circuits 37) permodule. Frequency divider circuit 113 is an electronic bistable circuitwhich may comprise conventional flip-flop circuits. Circuit 37a of FIG.9a includes the forward motion logic transfer circuitry of FIG. 8, but,in place of each of the lamps 64, 65, 66, a two-input gate circuit isemployed. Each two-input gate circuit comprises a pair of diodes 114,115 having a common connection at their cathodes. The anode of a firstof the pair of diodes 114 is connected to the input clock pulse +V buss28, and the anode of the second diode 115 is connected to the anode ofthe solid state device (67, 68 or 69) connected in circuit relationshiptherewith. The juncture of the cathodes of each pair of diodes isconnected to an electrical conductor 118 which is connected to the clockpulse +V input terminal 61 of the pulse generator and voltage switchcircuit 32 associated with each module (8-19) as shown in FIG. 9b. Theauxiliary circuit of FIG. 9a is thus an intermediate circuit forsequentially inhibiting the clock circuit pulses +V which are generatedby clock circuit 25 at the remote control console to thereby obtain thefreeze" control. A two position switch 119, which is connected at thepoint in the circuit 37a corresponding to the logic input V point of thelogic transfer circuits 37 in FIG. 8, is the device for initiatingoperation of the freeze" control circuit. Switch 119 may be actuated inresponse to a signal generated in a suitable command control circuitconveniently located at the remote control console. The freeze controloperates in the following manner: In the nonactuated normal (N) positionof switch 119, the gate circuit of solid state device 67 is grounded,and this zero voltage condition causes all of the solid state devices67, 68, 69 to be in a conducting state. Under such conditions, the clockpulses +V,; generated by clock circuit 25 are transmitted directly tothe clock pulse terminal 61 of each module byr-way of conductor 28,diode 114 of each two input gate circuit, and conductor 118. In theactuated freeze" (F) position of switch 119, the input to the gatecircuit of solid-state device 67 is connected to the switched voltage +Vcommon buss 57. At the moment that switch 119 is operated into thefreeze F position, all of the solid-state devices 67, 68, 69 are also ina conducting condition, but the next clock pulse +V which is di vided infrequency by six by circuit 113 causes nonconduction of solid-statedevice 67 and thus forward biases diode 114 of the two-input gatecircuit associated with solid-state device 67. The forward bias(conduction) of diode 114 supplies a DC level to the +V terminal 61 ofmodule 8 and prevents the pulse generator and voltage switch circuit 32thereof from transferring any further logic through such module, thatis, it freezes the logic state of module 8, regardless of any new logicinputs at the logic input terminal V in module 8.

The information input to information circuit 24 at the remote controlconsole must, of course, be correctly programmed to actuate switch 119at the desired time when the prescribed character has moved along thesign and reached the particular freeze" module. Thus, it must be knownwhich particular modules in the sign are connected in the freezing" modeof operation. For illustrative purposes only, it will be assumed that asign in FIG. 9b consists of 21 modules and that modules 8 through 19 canbe connected in the freezing" mode of operation. Module 1 represents theextreme left end of the sign as viewed by an observer, and module 21 theextreme right end, it being understood that the logic from theinformation circuit 24 enters the logic transfer circuits at module 21.The information input is so programmed that upon the first character (G)of a selected travelling message (GOOD MORNING) reaching the module (8)at which it is to be frozen, a command signal initiates operation ofswitch 119, disconnects it from the normal N position and reconnects itto the freeze F position. At this point in time, and during the intervalof the next six clock pulses, the first character (G) of the messagebecomes stationary in module 8, that is, becomes frozen as illustratedin FIG. 9(b)1. During the next six clock pulses, the remainingcharacters on the sign each advance one module as shown in FIG. 9(b)2,and the first letter 0 becomes frozen in module 9 since solidstatedevice 68 becomes nonconductive at this time. In like manner, the secondletter 0 becomes frozen in module 10 during the interval of the next sixclock pulses as illustrated in FIG. 9(b)3. It is readily apparent thatthe message to be frozen as programmed in the information input must bein double spaced form, as illustrated in FIG. 9(b)1, since during theinterval that one character is being frozen, the remaining unfrozencharacters continue to move along the sign in normal operation. Thus,every other character is eliminated in the freeze procedure wherein theclock pulses are divided by six as illus trated in FIG. 9a. In the moregeneral application, the characters eliminated will be proportional tothe division factor selected is component 113. Thus, if adivideby-twelve factor is used, two characters following each frozencharacter are eliminated. The eliminated characters are defined as thespaces on the sign which are between the characters that will beretained in the frozen state. These eliminated characters can be vacantspaces or any characters such as the XYZ illustrated in FIG. 9(b)lthrough 9(1))3. Therefore, a message can be disguised or modified byemploying this procedure.

In the operation of the freeze control, for each divided-by-sixfrequency clock pulse which operates circuit 32a of FIG. 9a, six normalfrequency clock pulses are supplied to the remaining unfrozen modules tocause normal logic transfer and thus normal travel of the charactersalong the sign. The successive groups of six clock pulses +V thusfinally freeze the complete GOOD MORNING message in modules 8 through 19as shown in FIG. 9(1))4. At a desired subsequent time, a

suitable command signal provided in the information input operatesswitch 119 into its normal N position and causes the frozen message tounfreeze. The unfreezing process causes modules 8 through 19 to besuccessively unfrozen in a manner similar to the freezing process. Thus,module 8 is first unfrozen during the first six clock pulses and causesthe first letter G to be advanced to module 7, the remaining modules9-19 remaining frozen as illustrated in FIG. 9(b)5. The second six clockpulses unfreeze module 9, cause the letter G and the first letter O tobe advanced one module, and modules 10-19 remain frozen as shown in FiG.9(b)6. In FIG. 9(b)7, the next six clock pulses unfreeze module 10,cause the letters GOO to be advanced one module each, and modules 11-19remain frozen. The remaining modules in the group 11 through 19 continueto be successively unfrozen by successive groups of six clock pulsesuntil the entire message is in the double spaced form as initiallypresented, as seen in FIG. 9(b)8.

An alternative freezing mode of operation involves the use of aswitching circuit 120 in the collector electrode circuit of transistor54, as well as switch 119. When switch 120 is in the freeze F position,no additional logic transfers or advances will occur in the freezecontrol" circuit of FIG. 9a, thus letters or messages of various lengthsmay be frozen or unfrozen by controlling the closure time of 120 withoutthe need for several separate +V input conductors.

The conventional method for displaying a travelling (moving) or changing(but nonmoving) message on the sign is to control the illumination ofthe lamps on a column-by-column basis as hereinabove described. It maybe desired, in the case of changing (but nonmoving) messages, to writethe message on a row-by-row basis. The circuit of FIG.'10 illustrates anarrangement for obtaining this row-by-row writing. FIG. 10 illustratesthree modules 21, 20, 19, having seven shift register circuits (sevenrows of logic transfer circuits) per module, similar to the moduleshereinabove described. The logic input (V V to each row of logictransfer circuits in the first module (module 21) is generated ininformation circuit 24 and supplied by means of conductors 27 as inFIG. 1. However, as distinguished from the modules in FIG. 1 wherein asingle pulse generator and voltage switch circuit 32 is provided for allseven rows of logic transfer circuits on a particular display panelsection or module, in FIG. 10 a separator pulse generator and voltageswitch circuit (not shown) must be provided for each row of logictransfer circuits in one module. In FIG. 10, a switching circuit 123 isconnected in the clock pulse input'(+V,. +V,. circuits to the pulsegenerator and voltage switch circuits 32 associated with each row oflogic transfer circuits. Switching circuit 123 includes six twopositionswitches, the nonactuated C position of the switches providingcolumn-by-column writing, and the actuated R position providingrow-by-row writing. The six switches are operated simultaneously inresponse to a signal generated in a column-row" command control circuit122 which may conveniently be located at the remote control console.

In the actuated R position of switching circuit 123, independent clockpulses V to V are supplied to each row. Thus, independent row-by-rowcontrol of logic switching is possible. If, for example, V to V clockpulses are not present, logic information will propagate only in thefirst row. After the first row is filled only V pulses might be allowedin order to fill the second row. This could be continued through theseventh row at which time the entire display would be filled to providea nonmoving display. In changing the message, either particular rowscould be moved out serially or all could be moved out simultaneously.For conventional operation as described in U.S. Pat. No. 3,384,888, thecolumn-row switch 123 is switched to the column-by-column writing Cposition by automatic command signals. thus providing identical Vstepping pulses for all rows and providing normal column-bycolumnwriting.

FIG. 11a illustrates a circuit for generating a new message while theold message is displayed on a changing (but nonmoving) message sign.This particular function is especially useful in minimizing the blanktime between messages and can only be obtained with logic transfercircuitry wherein the logic and power carrying circuits are not common.Therefore. the logic transfer circuits 37 of FIG. 8 cannot obtain thiswriting while hold" feature since in such circuits, the logic and powercarrying circuits are common. In FIG. 11a, a logic circuit 124 issimilar in construction to the logic circuit portion of the logictransfer circuit illustrated in FIG. 11 of U.S. Pat. No. 3,384,888, andlike numerals are employed to illustrate like terminals and elements inthe two circuits. The distinctions between the two circuits are that thephase controlled lamp intensity control voltage V, is not supplieddirectly into logic circuit 124 and the logic output V is connected inthe gate electrode circuit of the power carrying solid-state device 69.The circuit of FIG. further includes a transformer 150, the ends of thesecondary winding thereof being connected to the anodes of gatecontrolled solid state devices 151 and 152. The cathodes of devices 151and 152 have a common juncture and are connected to lamp 66. The gateelectrodes of devices 151 and 152 are supplied with the lamp intensitycontrol voltage V,-. The center tap of the secondary of transformer isconnected to the cathode of lamp power carrying solid state device 69 tocomplete the power circuit therefor. A switching circuit comprisingdiode 153, switch 154 and direct current source 155, is connected acrossthe serially connected lamp 66 and power carrying device 69. Switch 154is a two-position switch having a nonactuated "normal" (N) position andan actuated "write while hold (W) position.

Switch 154 is operated in response to a signal generated in a "writewhile hold" command control circuit 156 which may conveniently belocated at the remote control console.

The write while hold" circuit operation will now be described withspecific reference to FIGS. 11a and 11b.

Consider operation beginning at the time (i=0) when as displayed messageis to be changed. Write while hold" switch 154 is momentarily switchedto the nonactuated N position (sufficient time for one or more powerline zero crossings) which causes phase controlled lamp voltage V, to goto zero during the next power line voltage zero crossing. Thus, at t=0all lamp power solid state devices such as 69 are commutated off. Afterswitch 154 is switched to the actuated

1. A system for controlling multiple remote apparatus with a singleinformation channel link comprising a time-share transmitter forconverting information in a parallel seven bit format that controlsmultiple remote apparatus having a like parallel seven bit formatinformation input in parallel electrical pulse form to serial pulse formand for transmitting the serial pulse form information, and at least onetime-share receiver located remote from said transmitter for detectingthe transmitted serial pulse form information and for converting theserial pulse form information to parallel electrical pulse form, saidtime-share transmitter comprises a first one-shot multivibrator circuithaving an input supplied from a source of pulsed voltage having arepetition rate of one pulse per 50 milliseconds, each pulse periodincluding an initial off time of 0.2 millisecond the beginning of whichdetermines a transmitter reference zero time, said first multivibratorcircuit providing a 7.25 millisecond output pulse initiated at eachreference zero time, a triggered square wave generator circuit which istriggered into oscillatory operation by said first multivibrator circuitfor generating timing pulses at a one kilocycle per second rate, asecond one-shot multivibrator circuit, said second multivibrator circuitdirectly connected to an output of said square wave generator circuitand providing a 0.25 millisecond delay relative to the one kilocycle persecond timing pulses, the falling edges of the timing pulses initiatingsaid second multivibrator circuit and the rising edges of the secondmultivibrator pulsed output occurring 0.25 millisecond thereafter, aseven stage parallel-to-serial converter for converting data in sevenbit parallel electrical pulse form to serial electrical pulse form,output of said second multivibrator circuit connected to said sevenstage parallel-to-serial converter for advancing the converter one stageat a time corresponding to the rising edge of each 0.25 millisecondpulse, a first logic AND circuit, output of said square wave generatorcircuit directly connected to a first input of said AND circuit and thefalling edges of the 1 kilocycle per second timing pulses initiating theAND circuit, output of said converter connected to a second input ofsaid AND circuit, and a triggered pulse generator circuit provided witha first and second input, output of said square wave generator circuitdirectly connected to said first pulse generator circuit input forsupplying receiver synchronizing pulses thereto, the rising edges of the1 kilocycle per second timing pulses triggering said pulse generatorcircuit for effecting synchronization of the time-share receiver to thetime-share transmitter, output of said first AND circuit directlyconnected to said second pulse generator circuit input for supplying thedata in serial electrical pulse form thereto wherein the receiversynchronizing pulses and information pulses are time separated by 0.5milliseconds, the output of said time-share transmitter consisting ofseven synchronizing pulses equally spaced and up to seven informationbit pulses during the interval of each 7.25 milliseconDs pulse.